Memory Timing Guide
Posted 07-October-08 at 10:01 AM by THRiLL KiLL
So you want to get new memory for your system but are confused about the numbers? Here is a mini guide, compilated from info i found around the net.
What do the numbers mean? or in a more technical terms what does CAS-TRCD-TRP-TRAS mean?
CAS Latency
Certainly, one of the most important timings is the CAS Latency, which is also the one most people understand. Since data is often accessed sequentially (same row), the CPU need only select the next column in the row to get the next piece of data. In other words, CAS Latency is the delay between the CAS signal and the availability of valid data on the data pins (DQ). The latency between column accesses (CAS) then plays an important role in the performance of the memory. The lower the latency, the better the performance. However, the memory modules must be able to support low-latency settings.
Example: 2.5-3-3-8 The bold 2.5 is the CAS timing.
tRCD
tRCD is the delay from the time a row is activated to when the cell (or column) is activated via the CAS signal and data can be written to or read from a memory cell. When memory is accessed sequentially, the row is already active and tRCD will not have much impact. However, if memory is not accessed in a linear fashion, the current active row must be deactivated and then a new row selected/activated. In such an example, low tRCD's can improve performance. However, like any other memory timing, putting this too low for the module can cause in instability.
Example: 2.5-3-3-8 The bold 3 is the tRCD timing.
tRP
tRP is the time required to terminate one row access and begin the next row access. tRP might also be seen as the delay required between deactivating the current row and selecting the next row. So in conjunction with tRCD, the time required (or clock cycles required) to switch banks (or rows) and select the next cell for reading, writing, or refreshing is a combination of tRP and tRCD.
Example: 2.5-3-3-8 The bold 3is the tRP timing.
tRAS
tRAS is the time required before (or delay needed) between the active and precharge commands. In other words, how long the memory must wait before the next memory access can begin.
Example: 2.5-3-3-8 The bold 8 is the tRAS timing.
RAS
Memory architecture is like a spreadsheet with row upon row and column upon column, with each row being one bank. For the CPU to access memory, it first must determine which row or bank in the memory is to be accessed and then activate that row with the RAS signal. Once activated, the row can be accessed over and over, until the data is exhausted. This is why tRAS has little effect on overall system performance but could impact system stability if set incorrectly.
tCLK
This is simply the clock used for the memory. Note that because frequency is 1/t, if memory were running at 100Mhz, the timing of the memory would be 1/100Mhz, or 10nS.
So obliviously the lower the numbers on the memory.. the faster the memory, right? yes and no.
when you look at memory you also need to look at the memory bandwidth. yes a stick of pc133 2-3-3-4 might seem faster then a stick of pc800 4-4-4-12, as it has lower memory timings, but another factor comes into play. The memory bandwidth. The more bandwidth the memory has the faster it goes, but at the same time the latency goes up. To keep memory prices lower, manufactures will have much slower timings on the memory, but due to the massive bandwidth the memory over all is faster.
What do the numbers mean? or in a more technical terms what does CAS-TRCD-TRP-TRAS mean?
CAS Latency
Certainly, one of the most important timings is the CAS Latency, which is also the one most people understand. Since data is often accessed sequentially (same row), the CPU need only select the next column in the row to get the next piece of data. In other words, CAS Latency is the delay between the CAS signal and the availability of valid data on the data pins (DQ). The latency between column accesses (CAS) then plays an important role in the performance of the memory. The lower the latency, the better the performance. However, the memory modules must be able to support low-latency settings.
Example: 2.5-3-3-8 The bold 2.5 is the CAS timing.
tRCD
tRCD is the delay from the time a row is activated to when the cell (or column) is activated via the CAS signal and data can be written to or read from a memory cell. When memory is accessed sequentially, the row is already active and tRCD will not have much impact. However, if memory is not accessed in a linear fashion, the current active row must be deactivated and then a new row selected/activated. In such an example, low tRCD's can improve performance. However, like any other memory timing, putting this too low for the module can cause in instability.
Example: 2.5-3-3-8 The bold 3 is the tRCD timing.
tRP
tRP is the time required to terminate one row access and begin the next row access. tRP might also be seen as the delay required between deactivating the current row and selecting the next row. So in conjunction with tRCD, the time required (or clock cycles required) to switch banks (or rows) and select the next cell for reading, writing, or refreshing is a combination of tRP and tRCD.
Example: 2.5-3-3-8 The bold 3is the tRP timing.
tRAS
tRAS is the time required before (or delay needed) between the active and precharge commands. In other words, how long the memory must wait before the next memory access can begin.
Example: 2.5-3-3-8 The bold 8 is the tRAS timing.
RAS
Memory architecture is like a spreadsheet with row upon row and column upon column, with each row being one bank. For the CPU to access memory, it first must determine which row or bank in the memory is to be accessed and then activate that row with the RAS signal. Once activated, the row can be accessed over and over, until the data is exhausted. This is why tRAS has little effect on overall system performance but could impact system stability if set incorrectly.
tCLK
This is simply the clock used for the memory. Note that because frequency is 1/t, if memory were running at 100Mhz, the timing of the memory would be 1/100Mhz, or 10nS.
So obliviously the lower the numbers on the memory.. the faster the memory, right? yes and no.
when you look at memory you also need to look at the memory bandwidth. yes a stick of pc133 2-3-3-4 might seem faster then a stick of pc800 4-4-4-12, as it has lower memory timings, but another factor comes into play. The memory bandwidth. The more bandwidth the memory has the faster it goes, but at the same time the latency goes up. To keep memory prices lower, manufactures will have much slower timings on the memory, but due to the massive bandwidth the memory over all is faster.
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