Part I of this series covered Microsoft's vision for dynamic content creation in the next generation of console games. In this article, Part II, we take a closer look at this CPU, codenamed Xenon. We cover the design of its individual parts, and we'll talk about how each part fits with the vision outlined in Part I.




Instead of spending hardware on an instruction window that looks for ILP at run-time, the Xenon instead relies on the programmer to structure the code stream at compile time so that it contains a high level of thread-level parallelism (TLP). In order to take advantage of the high level of TLP that the Xenon expects programmers to have worked into their Xbox 360 applications, the processor groups its large number of execution units into three separate cores, each of which individually contains a relatively small number of execution units. The many parallel threads out of which the programmer has woven the code stream are then scheduled to run on those separate cores.




The architecture of the individual PowerPC processor cores that make up the Xenon is covered in as much detail as is currently possible, and we also pull together what is known about the high-powered, 128-register vector unit that forms the heart of the Xenon's procedural synthesis capabilities.
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